`timescale 1ns / 1ns

module tb();

reg clkin;
wire sys_sta;
wire dac0_clk;
wire dac1_clk;
reg sys_rst_n;
wire [7:0] dac0_data;
wire [7:0] dac1_data;

reg usb_clk_60m;
reg usb_rxf_n;
reg [7:0] data_cnt;
reg [7:0] usb_60m_clk_cnt;
wire [7:0] usb_data;
wire usb_oe_n;
wire usb_rd_n;

initial begin
    clkin = 1'b1;
    usb_clk_60m = 1'b1;
    usb_rxf_n = 1'b1;
    sys_rst_n <= 1'b0;
    data_cnt <= 1'b0;
    usb_60m_clk_cnt <= 8'd32;
    #200
    sys_rst_n <= 1'b1;
end

GSR GSR(.GSRI(1'b1));

always #20 clkin <= ~clkin;
always #33 usb_clk_60m <= ~usb_clk_60m;
always #1000000 usb_60m_clk_cnt <= 'b0;

always @(negedge usb_clk_60m) begin
    if ((usb_60m_clk_cnt < 8'd32) && sys_rst_n)
        usb_60m_clk_cnt <= usb_60m_clk_cnt + 8'd1;
    else
        usb_60m_clk_cnt <= usb_60m_clk_cnt;
end

always @(negedge usb_clk_60m) begin
    if ((usb_60m_clk_cnt < 8'd32) && sys_rst_n)
        usb_rxf_n = 1'b0;
    else
        usb_rxf_n = 1'b1;
end

always @(posedge usb_clk_60m) begin
    if ((!usb_oe_n) && (!usb_rxf_n))
        data_cnt <= data_cnt + 1'd1;
    else
        data_cnt <= 8'd0;
end

assign usb_data = (!usb_oe_n) ? data_cnt : 8'hzz;

PrjGieGieGowinDualDaStreamer u_bd (
    .sys_rst_n      (sys_rst_n),
    .sys_clk        (clkin),
    .sys_sta        (sys_sta),
    .dac0_clk       (dac0_clk),
    .dac1_clk       (dac1_clk),
    .dac0_data      (dac0_data),
    .dac1_data      (dac1_data),
    // FT232H
    .usb_clk_60m (usb_clk_60m),
    .usb_rxf_n (usb_rxf_n),
    .usb_data (usb_data),
    .usb_oe_n (usb_oe_n),
    .usb_rd_n (usb_rd_n)
);

endmodule